Supply voltage (VDD) and threshold-voltage (VT) have to be co-optimized to minimize the switching and leakage power in a processor. This co-optimization depends on both the application performance requirements and the circuits' switching activity factor. However, with power management techniques of dynamic voltage-frequency scaling and clock-gating becoming popular, a basic VDD-VT optimization procedure is not possible since they need to use the same hardware (i.e., same VT) but may have very different performance requirements and different activity factors.